1. Technical Field
The present invention relates to semiconductor memory devices and, more specifically, to semiconductor memory devices which are testable with a single data rate (SDR) and/or dual date rate (DDR) pattern in a merged data input/output pin (DQ) test mode.
2. Discussion of the Related Art
Testing semiconductor memory devices can be divided into two procedures when fabricating from raw wafers to completely packaged products. One procedure is a wafer test for detecting defects on a wafer where semiconductor chips have been manufactured. Another procedure is a package test for detecting defects in packaged products after the wafer test. Semiconductor products subject to these test procedures may typically be required to satisfy prior design specifications.
These design specifications tend to increase the number of input/output pins in semiconductor memory devices because of the need for higher capacities, integration densities, and facilities. Usually a test procedure is conducted by comparing actual data with expected (or desired) data by connecting the input/output pins of a semiconductor memory device to the channels of a tester (or testing equipment). Based on the comparison result, one may determine whether or not there is a defect in the tested semiconductor memory device. Even though a large number of test channels are found in a typical tester, the increasing number of input/output pins in common semiconductor memory devices may reduce the number of semiconductor memory devices capable of being tested at one time by a tester. In addition, the increasing number of input/output pins relative to the limited number of test channels may increase test time for the semiconductor memory devices and thereby, increase the cost of the test and reduce the productivity of the tester.
In order to overcome the limited number of test channels in a tester versus the number of input/output pins in a semiconductor memory device, a merged DQ test scheme has been proposed. The merged DQ test scheme assigns the input/output pins (e.g., DQ pins) of a memory device to a single pin of a tester. Data bits to be output through a plurality of DQ pins are internally compared with each other (or an expected data bit), and then, as a single bit, the comparison result is output to the single pin of the tester. By unifying a plurality of DQ pins to a single test channel (or a single test pin) the number of semiconductor memory devices testable is increased and the test cost is reduced.
FIG. 1 illustrates an example of the merged DQ test scheme for use with a semiconductor memory device. A semiconductor memory device 100 to be tested is comprised of data latches 110, a data comparator 130, a data combiner 150, a merging controller 170, and output buffers 180 (including buffers 190-198). The data latches 110 hold internal data bits I/O0-I/O8 of the memory device 100, in response to an internal clock signal KCORE. The internal data bits I/O0-I/O8 in the data latches 110 are transferred to the output buffers 180 through de-multiplexers DMUX during an inactive state of a merging signal MDQ and through the data comparator 130 during an active state of the merging signal MDQ. In a normal operation mode, not a test mode, the output buffers 180 output the latched data bits I/O0-I/O8 through DQ pads (DQ0-DQ8) (or pins).
In a merged DQ test mode, the data comparator 130 compares the latched data bits I/O0-I/O8 to each other and then transfers the comparison results to the data combiner 150. In the data combiner 150, the comparison results are put into an exclusive-OR (XOR) logic circuit and an output of the XOR logic circuit is applied to the merging controller 170 as an output DOUTMDQB in response to the merging signal MDQ. The merging controller 170 transfers its own output DOUTMDQ to one of the output buffers 190-198, e.g., output buffer 195, in response to an output clock signal KDATA and a merging flag signal MFLAG. An output from the output buffer 195 is transmitted to its corresponding DQ pad DQ5 by control of an output enable generator that responds to the merging signal MDQ and provides an output enable signal to permit data to be output to the output buffer's 195 DQ pad DQ5. Therefore, the DQ pad DQ5 selected as an output terminal for the merged data bit becomes a merged DQ pad in the merged DQ test mode.
The data combiner 150 generates two outputs: one is a first merging data bit DOUTMDQB_W that is active at a rising edge of the clock signal; the other is a second merging data bit DOUTMDQB_X that is active at a falling edge of the clock signal. Referring to FIG. 2, which shows a circuit diagram of the merging controller shown in FIG. 1, in the merging controller 170, the first and second merging data bits, DOUTMDQB_W and DOUTMDQB_X, alternatively trigger the output DOUTMDQ in response to output clock signals KDATA_W1 and KDATA_X1, respectively when the merging flag signal MFLAG is active with a high level logically.
During this procedure, the output DOUTMDQ of the merging controller 170 is conductive in an SDR mode because the output clock signals KDATA_W1 and KDATA_X1 are not simultaneously enabled even though the merging data bits DOUTMDQB_W and DOUTMDQB_X are conductive in a DDR mode. Thus, the merging controller 170 does not operate in the DDR mode, rather it operates in the SDR mode while the data combiner 150 is operable in the DDR mode.
Therefore, the merged DQ test scheme with the merging controller shown in FIG. 2 is unavailable in the DDR mode required for high bandwidth synchronous semiconductor memory devices.